drivers: clock_control: stm32 ll common: fix RCC pll disable #83062
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Hello @bbyers-UBCO, and thank you very much for your first pull request to the Zephyr project! |
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Thanks @bbyers-UBCO !
Please fix the compliance issues reported by ci here.
| /* Disable PLL */ | ||
| LL_RCC_PLL_Disable(); | ||
| while (LL_RCC_PLL_IsReady() != 0U) { |
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Please fix indentation (we're using 8 char tabs)
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Fixed. Also added the LL_RCC_PLL2_IsReady() check as @FRASTM mentioned.
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The clock_stm32_ll_common.c function set_up_plls calls LL_RCC_PLL_Disable();and it was not waiting for the disable to complete before trying to configure the pll sysclock which creates a race condition for pll configuration.The wait for re-enabling the RCC pll is already there, it was just missing the wait for the disable before configuration. Also added the wait for PLL2. Signed-off-by: Benjamin Curtis Byers <[email protected]>
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The clock_stm32_ll_common.c function set_up_plls calls LL_RCC_PLL_Disable(); and it was not waiting for the disable to complete before trying to configure the pll sysclock which creates a race condition for pll configuration. The wait for re-enabling the RCC pll is already there, it was just missing the wait for the disable before configuration.